TECHNOLOGY AREA(S): Electronics, Information Systems, Sensors

ACQUISITION PROGRAM: ESM and SIGINT 6.3a program are target audience

OBJECTIVE: Increase the analog to digital convertor (ADC) Spurious-free Dynamic Range (SFDR) by 10 dB by digitally diminishing the predictable spurs. Wideband Si and SiGe ADCs often incorporate substantial on-chip linearization processing. In contrast, superconducting ADCs are not today linearized and exhibit spurs as large as 15 dB above the inherent quantization noise floor.

DESCRIPTION: This STTR topic requires a deep understanding of the nature of quantization errors in low bit count, high-speed digitizers and the interdependence of time and frequency domain signal representations. However, no details of the exact ADC will be provided and no run-time dynamic adaptation of the circuit will be acceptable. Rather proposers are expected to correct the output data stream in real time using only digital processors. Two types of distortions of the frequency domain output of ADCs are of concern: a) fixed subharmonics of the sampling clock engendered by rapid switching transients in the output drivers weakly (~-30 dB down) coupled to the analog signal inputs; and b) harmonics of the signal fundamentals, some of which reflect the actual quantization errors associated with the limited bit width samples. The topic philosophy is that the clock spurs are at entirely predictable and consistent frequencies. While their relative amplitudes might depend on the signal mix being digitized at any given time, that will change relatively slowly and some form of interference cancellation/background subtraction ought to be applicable. Achieving that should be the first goal of the effort. Then in the 3 bit, 40 GSps ADCs of greatest interest, there is a range of signal amplitudes where a Fourier Transform shows as many as 18 harmonics above the quantization noise floor, but not any other mixing products (e.g., with the clock). It is for a smaller signal amplitude range such that maybe only 5 harmonics break the noise floor that the second goal applies. Namely, these harmonics in part reflect the inaccuracies of the real quantization levels in comparison to the actual time dependent signal shape and in part systematic errors in the threshold levels compared to their optimal selection. As such, constructively using the harmonic signals observed ought to provide a way of making the signal representation output more accurate. The real thermal noise that is being quantitized must be distinguished from these systematic terms but is expected to be a small contribution to the total spur power. Recorded data of an actual ADC's response to various amplitude and frequency sine waves can be provided as government furnished information (GFI) for software training purposes if the proposer so requests. Artificial intelligence (AI) and machine learning (ML) are assumed to be the sources of potential solutions due to their ability to learn systematic behavior without supervision. However, any other approach capable of keeping up with the ADC results arrival rate may be proposed. Processing latencies of less than 1 millisecond and reduction of the effective spurs by more than 6 dB are sought.

PHASE I: In the Phase I proposal, define a definite plan of attack to be conducted and clarify the balance between proposed tasks. The proposal should also define a mechanism for selecting the more successful one if more than one approach is to be attempted, include a clear Gannt chart of the proposed tasks, and� indicate whether the contractor or sub-contractor is responsible for each task. Inclusion of a discussion of test plans is desirable. Any need for GFI and its data ingest format should also be carefully described. The Phase I Base effort needs to work the concepts/tasks defined in the original proposal so as to significantly lower the risk of success if a follow-on award is offered. The preliminary Phase II proposal delivered at the end of the Base effort will be used to select the Phase II winner. The Phase I Option should be structured to further lower the technical risk of Phase II assuming the approach of the Base succeeds. If any approaches prove unworkable, the topic author(s) should be consulted before the approach is changed. The provisional Phase II plan delivered at the end of the base Phase I Base period will determine whether each performer is awarded a Phase II contract. If selected for Phase II, the Phase I Option period will then be exercised. It should provide continuity until the Phase II begins and further reduce technical risk of the proposed overall approach. Phase II is when the claim of real time processing needs to be developed/demonstrated.

PHASE II: Conduct a working experimental demonstration of spectral clean up by the developed signal processing in the labs of the Government or the ADC vendor to demonstrate real-time processing. Quantification of the degree of real-time spur reduction achieved as a function of sampling clock frequency is expected. The Government will help arrange that testing late in the Phase I Base period.

PHASE III DUAL USE APPLICATIONS: By the end of this STTR effort, the ADC in question ought to have transitioned into fielded systems. Hence once this software is proven useful, it can be added into the digital signal processing (DSP) portion of such systems and result in higher accuracy situational awareness reports to the warfighter. Outside the DoD, the resultant software is expected to be the first linearization product that directly addresses frequency domain issues following a time domain digitizer and could be one of the earliest systems to combine AI with ML in a hybrid, directed system architecture. Examples in other application domains, including correcting for amplifier distortion, ought also to be possible. Specific commercial markets could include satellite communications and many band 5G wireless networks in addition to laboratory instrumentation.

REFERENCES:

1. Yang, Y.-, Motafakker-Fard, A. and Jalali, B. "Linearization of ADCs via digital post processing." 2011 IEEE International Symposium on Circuits Systems, May 15-18, 2011, Rio de Janeiro, Brazil. https://ieeexplore.ieee.org/document/5937734

2. Hummels, D. "Performance improvement of all-digital wide-bandwidth receivers by linearization of ADCs and DACs." Science Direct, Measurement, 4th Workshop on ADC Modelling and Testing, Vol. 31, Issue 1, January 2002, pp. 35-45. https://www.sciencedirect.com/science/article/pii/S0263224101000124

3. Zhang, T., Cao, Y.,� Ye, F. and Ren, J. "Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC." 2018 IEEE International Symposium on Circuits Systems (ISCAS), May 27-30, 2018, Florence, Italy. https://ieeexplore.ieee.org/document/8350904

4. Tatsumi, K., Matsuoka, T. and Tani, S. "A calibration with an adaptive data selection based on Bayes estimation for a successive stochastic approximation ADC system." 2017 Joint 17th World Congress of International Fuzzy Systems Association and 9th International Conference on Soft Computing and Intelligent Systems (IFSA-SCIS), June 27-30, 2017, Otsu, Japan. https://ieeexplore.ieee.org/document/8023246

5. Danial, L., Wainstein, N., Kraus and Kvatinsky, S. "Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture." IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 2, no. 5, pp. 396-409, Oct. 2018. https://ieeexplore.ieee.org/document/8471014

KEYWORDS: Linearization; Deterministic Phenomena; Cross Talk; Artificial Intelligence; Frequency Domain Learning; Harmonic Expansion; Probabilistic Comparator Behavior; Equalization Error; Machine Learning; ML; AI